The invention pertains in general to a method for manufacturing a semiconductor device and, more particularly, to a method for providing an anti-reflective coating layer having a uniform thickness during a dual damascene process.
In the semiconductor manufacturing process, one or more metal layers are formed to serve as interconnects between active devices formed on a semiconductor wafer and the outside world. The metal layers are separated from each other by insulating layers. Damascene is an interconnect fabrication process that provides a plurality of horizontal grooves on an insulating layer. The grooves are filled with metal to form conductive lines. Dual damascene is a multi-level interconnect process that, in addition to forming conductive lines, forms conductive vias that connect the metal layers. The conductive vias also connect other conductive regions, such as the gate, source and drain regions, of the active devices to one or more of the metal layers.
In a conventional dual damascene process, a first photoresist is generally provided over an insulating layer. A first mask with patterns of vias is then provided over the first photoresist to define and pattern the first photoresist. The insulating layer is etched, and vertical openings for the vias are formed in the insulating layer. After the first photoresist is removed, the insulating layer is coated with a layer of anti-reflection coating (xe2x80x9cARCxe2x80x9d) and the vertical openings are filled with the ARC material. A second photoresist is provided over the ARC layer. A second mask with patterns of the conductive lines is used to define and pattern the second photoresist. After the second photoresist is defined and developed, the second photoresist, ARC layer, and insulating layer are etched. Horizontal grooves for the conductive lines are formed in the ARC layer and on the upper portion of the insulating layer. The second photoresist is stripped, and the ARC layer, including the ARC material provided in the vertical openings, is removed. The grooves and vertical openings are then filled with metal, such as tungsten or copper. The resulting surface is then planarized through chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d).
During the photolithographic process, light passes through a photoresist film down to the semiconductor substrate, where the light is reflected back up through the photoresist. The reflected light could interfere with the adjacent photoresist, adversely affecting the control of the critical dimension (xe2x80x9cCDxe2x80x9d) of the manufacturing process. The ARC material is used to suppress unintended light reflection from a reflective surface that is beneath the photoresist. However, when the ARC material is used to fill the vertical openings, the local thickness of the ARC layer over the top surface of the underlying layer varies, depending upon the via pattern and density. As a result, the ARC layer may exhibit non-uniformity in its thickness across the underlying layer as shown in FIG. 1.
Referring to FIG. 1, an ARC layer 102 is provided over an underlying layer 100, which includes a plurality of vertical openings 104 filled with the ARC material. The ARC layer 102 provided over the region of the underlying layer 100 having a dense via pattern region is thinner compared to the region of the layer 100 having an isolated via pattern region. The non-uniformity of the ARC layer thickness may result in unintended increase in the CD.
More specifically, referring to FIG. 2A, a dielectric layer 106 is formed over a substrate 101 with a plurality of semiconductor devices (not shown). A first layer of patterned photoresist (xe2x80x9cPRxe2x80x9d, not shown) is then provided over dielectric layer 106. The first patterned PR layer is used as a mask to form a plurality of via openings 108 in dielectric layer 106. After removal of the first patterned PR layer, a bottom anti-reflective coating (xe2x80x9cBARCxe2x80x9d) layer 110 is formed over substrate 101, and via openings 108 are filled with BARC layer 110. The thickness of BARC layer 110 across the top surface of the underlying dielectric layer 106 varies due to changes of density of via openings 108. Specifically, BARC layer 110 provided over region 102 having denser via openings is thinner compared to region 104 having less dense via openings.
Referring to FIG. 2B, a second PR layer 112 is provided over BARC layer 110. After second PR layer 112 is defined and developed, layer 112 and BARC layer 110 are etched to form a plurality of openings 114 to define trenches generated thereafter. Patterned PR layer 112 is then used as a mask to remove exposed BARC layer 110. Because BARC layer 110 is thicker in region 104 than in region 102, to completely remove the exposed BARC layer 110 of openings 114 in region 104, etching time must be increased. However, increasing etching time results in widening of openings 114 in region 102 from dimension xe2x80x9caxe2x80x9d to xe2x80x9cbxe2x80x9d.
Referring to FIG. 2C, a plurality of trenches 116 are formed by further etching dielectric layer 106, wherein PR layer 112 is used as a mask. PR layer 112 and BARC layer 110 over dielectric layer 106 and in via openings 108 are removed. Next, via openings 108 and trenches 116 are filled with conductive material 118 to complete the dual damascene process. Again, unintended deviation of CD of trenches 116 from xe2x80x9ccxe2x80x9d to xe2x80x9cdxe2x80x9d in region 102 will occur, and this phenomenon may lead to electrical shorts between adjacent lines, and even to device failure.
In accordance with the invention, there is provided a method for manufacturing a semiconductor device that includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trenches in the dielectric layer.
Also in accordance with the present invention, there is provided a method of manufacturing a dual damascene device that includes forming a plurality of active devices over a substrate, providing a layer of dielectric material over the active devices and the substrate, providing a plurality of vertical openings in the layer of dielectric material, wherein at least one of the plurality of vertical openings extends through to one of the plurality of active devices, depositing a first photoresist layer over the layer of dielectric material, the first photoresist layer filling the plurality of vertical openings, etching the first photoresist layer such that the first photoresist layer has a first substantially uniform thickness over the dielectric layer, and depositing an anti-reflection coating layer over the first photoresist layer.
In accordance with the present invention, there is additionally provided a method of manufacturing a dual damascene device that includes forming a plurality of active devices over a substrate, providing a layer of dielectric material over the active devices and the substrate, providing a plurality of vertical openings in the layer of dielectric material, wherein at least one of the plurality of vertical openings extends through to one of the plurality of active devices, depositing a first photoresist layer over the layer of dielectric material, the first photoresist layer filling the plurality of vertical openings, etching the first photoresist layer such that the first photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the first photoresist layer, providing a second photoresist layer over the anti-reflection coating layer, patterning and defining the second photoresist layer, etching the anti-reflection coating layer and the first photoresist layer to form a plurality of trenches in the layer of dielectric material, removing the first photoresist layer, the anti-reflection coating layer and the second photoresist layer, and providing metal to the plurality of vertical openings and plurality of trenches.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.